Cache Hits and Cache Misses Explained for IB Computer Science

• The CPU must request the data from RAM
• The data is transferred from RAM to the cache
• The CPU then accesses the data from cache

This process takes significantly longer than a cache hit.

IB examiners expect students to recognise that:

• Cache misses slow down execution
• Cache misses are unavoidable but should be minimised

Types of Cache Misses (HL Awareness)

At a higher level, students may be aware that cache misses occur for different reasons, such as:

• Data not yet loaded into cache
• Cache being too small
• Previously cached data being replaced

However, IB students are not expected to memorise advanced classifications — understanding the general concept is sufficient.

How Cache Improves Performance Overall

Even though cache misses occur, cache is effective because:

• Programs often reuse the same data
• Instructions are frequently accessed repeatedly
• Loops benefit heavily from caching

This behaviour means that most data requests result in cache hits, not misses.

Cache Hits, Cache Misses, and the Fetch–Decode–Execute Cycle

During the fetch stage:

• Instructions may be fetched from cache instead of RAM
• A cache hit speeds up instruction retrieval
• A cache miss introduces delay

This directly links cache behaviour to CPU performance.

Common Student Mistakes

Students often:

• Confuse cache with RAM
• Say cache permanently stores data
• Ignore the performance impact of misses
• Fail to explain what happens after a miss

Precise cause-and-effect explanations are required.

Final Thoughts

Cache hits and cache misses explain why cache memory is so important in modern computers. Cache hits allow the CPU to run at high speed, while cache misses introduce delays by forcing access to RAM.

Understanding this balance helps IB Computer Science students explain system performance clearly and accurately — exactly what examiners are looking for.

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